ESE provides a service to support design and verification methodologies for Application-Specific-Integrated-Circuits (ASICs). As a community, we are already benefiting from the careful and thorough adoption of such techniques in the preparation of designs for the HL-LHC upgrades. Examples include developments for several experiment-dedicated and common chips. However, these techniques are still not applied systematically to all large-scale ASIC designs for HEP experiments. The CERN-HEP IC design Platform and Services (CHIPS) programme aims to address this issue with active support to the community. A more detailed overview of CHIPS is available here.



The CHIPS website is here.