The CMS High Granularity Calorimeter (HGCAL).

A major upgrade in the CMS detector is to replace the current end cap calorimeters (ECAL and HCAL) with a new “High Granularity Calorimeter“ or HGCAL.

The HGCAL is a very ambitious project. Unusually for a calorimeter it is able to track particles in a 3D volume as well as measure energy deposition. It is built as a large sampling calorimeter. It has around 50 layers of high granularity sensors interleaved with absorber materials. Two sensor materials are used; silicon in the higher radiation regions and scintillating tiles in the lesser radiation regions. In total there will be ~600 m2 of silicon sensors and 500 m2 of scintillating tiles. 
The Electromagnetic region (CE-E) will be all silicon whilst the Hadronic part (CE-H) will be a mixture of silicon and scintillating tiles. The operating temperature will be -30 degrees C.

The silicon sensors are hexagonal in shape and are mounted on silicon modules. 

The charge from the sensor is readout (at every bunch crossing) by the front-end ASIC (HGCROC). Each HGCROC has 72 active channels. The HGCROC is capable to readout and digitize the sensor charge over a very wide dynamic range. It does this in two parts. The lower part of the dynamic range is sampled by a 10b SAR ADC. The upper range is digitized using a Time Over Threshold technique. The time of arrival (TOA) is also measured and digitized by a 10b TDC.  Following this initial analog sampling stage, the HCGROC splits the data into two paths (a trigger path and a data path). The trigger path computes trigger primitives which are sent out in real time on 4 x 1.28 Gbps outputs. The data path on the other hand buffers the sampled data until receipt of a first level trigger ( LV1A). The triggered events are assembled into data packets and sent out over 2 outputs at 1.28 Gbps. Control of the chip is done via I2C for slow control programming of internal registers and by 320 Mbps Clock and T1 Fast Command inputs.

The two output paths from HGCROC (Trigger and Data) are sent to two digital ASICs, namely ECON-T and ECON-D. 
ECON-T receives the trigger primitives from HGCROC. It selects and compresses interesting HGCROC trigger data according to preprogrammed trigger algorithms.  It does this in real time and transmits the selected and compressed trigger information for every bunch crossing at 40MHz. The ECON-T has 12 1.28Gbps inputs and up to 14 1.28Gbps outputs. The outputs then connect to lpGBTs for optical transmission off the detector.
ECON-D receives the triggered historical data from HGCROC. It performs zero suppression and concentration of the data before transmission off chip at rates up to the LV1A maximum trigger rate of 750kHz. Once again using the lpGBT for optical transmission.

Within the HGCAL system there are ~ 100,000 HGCROC chips which are mounted directly on the Hexaboards of the silicon modules. The HD silicon modules have 6 HGCROC chips and the LD modules have 3. Each silicon module is equipped with an ECON mezzanine hosting ECON-D and ECON-T chips. There are approximately 27000 modules in the silicon region. 
The scintillator region has very similar electrical system configuration with HGCROCs and ECONs.

Other ASICs used in the HGCAL electronics system are : Rafael, bPOL DCDC devices, LDOs,  lpGBT, VTRX+ and GBTSCA.