The FastRICH is a readout chip that is being designed by EP-ESE and collaborators in the framework of the upgrade of the LHCb RICH detector to be installed during the LHC Long Shutdown 3 (2026-2028). It will read out multi-anode PMTs, while allowing compatibility with a detector R&D programme for operation in Run 5 for which SiPMs are candidates. The Application Specific Integrated Circuit (ASIC) is a derivative of the FastIC ASIC designed in collaboration between the Microelectronics section at CERN and the University of Barcelona.

More information on FastRICH is available here.